60-GHz CMOS Phase-Locked Loops

60-GHz CMOS Phase-Locked Loops


The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market.

60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.

Table of contents

Front Matter....Pages i-viii
Introduction....Pages 1-9
Synthesizer System Architecture....Pages 11-34
Layout and Measurements at mm-Wave Frequencies....Pages 35-55
Design of High Frequency Components....Pages 57-149
Design of Low Frequency Components....Pages 151-164
Synthesizer Integration....Pages 165-181
Conclusions....Pages 183-184
Back Matter....Pages 185-197


  • Author: Hammad M. Cheema, Reza Mahmoudi, Arthur H. M. Roermund (auth.)
  • Edition: 1
  • Publication Date: 2010
  • Publisher: Springer Netherlands
  • ISBN-10: 904819279X
  • ISBN-13: 9789048192793
  • Pages: 206
  • Format: pdf
  • Size: 3.2M
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