3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme

3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme

Description

"3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme"elaborates the concept and importance of 3-Dimensional (3-D) VLSI. The authors have developed a new 3-D IC integration paradigm, so-called 2.5-D integration, to address many problems that are hard to resolve using traditional non-monolithic integration schemes. The book also introduces major 3-D VLSI design issues that need to be solved by IC designers and Electronic Design Automation (EDA) developers. By treating 3-D integration in an integrated framework, the book provides important insights for semiconductor process engineers, IC designers, and those working in EDA R&D.

Dr. Yangdong Deng is an associate professor at the Institute of Microelectronics, Tsinghua University, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor at the Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.

Table of contents

Cover......Page 1
3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme......Page 2
Title Page ......Page 3
ISBN 9783642041563......Page 4
Preface......Page 7
Acknowledgements......Page 9
Table of Contents ......Page 11
List of Figures and Tables......Page 15
1 Introduction......Page 19
1.1 2.5-D Integration......Page 23
1.2.1 Fabrication Technology......Page 26
1.2.2 Testing Methodology and Fault Tolerance Technique......Page 27
1.2.3 Design Technology......Page 28
1.3 Objectives and Book Organization......Page 31
References......Page 34
2 A Cost Comparison of VLSI Integration Schemes......Page 39
2.1 Non-Monolithic Integration Schemes......Page 40
2.1.2 Multiple Chip Module (MCM)......Page 41
2.1.3 Three-Dimensional (3-D) integration......Page 42
2.2 Yield Analysis of Different VLSI Integration Approaches......Page 44
2.2.2 Multiple-Reticle Wafer (MRW)......Page 46
2.2.3 Three-Dimensional (3-D) Integration......Page 48
2.2.4 2.5-D System Integration......Page 49
2.2.5 Multi-Chip Module......Page 52
2.2.6 Summing Up......Page 53
2.3 Observations......Page 55
References......Page 56
3 Design Case Studies......Page 60
3.1 Crossbar......Page 61
3.2.1 Tackle the Long Bus Wire......Page 64
3.2.2 Serialized Channel in the 3rd Dimension......Page 66
3.3 A 2.5-D Redesign of PipeRench......Page 68
3.3.1 The 2.5-D Implementation......Page 70
3.3.2 Simulation Results......Page 72
3.4 A 2.5-D Integrated Microprocessor System......Page 74
3.4.1 A 2.5-D Integrated Microprocessor System......Page 75
3.4.2 An Analytical Performance Model......Page 80
3.4.3 Detailed Performance Simulation for Reduced Memory Latency......Page 84
3.5 Observations......Page 87
References......Page 89
4 An Automatic 2.5-D Layout Design Flow......Page 92
4.1 A 2.5-D Layout Design Framework......Page 93
4.1.1 2.5-D Floorplanning......Page 95
4.1.3 2.5-D Global Routing......Page 96
References......Page 99
5 Floorplanning for 2.5-D Integration......Page 101
5.1.1 Technique......Page 105
5.1.2 Results......Page 107
5.2.1 Technique......Page 109
5.2.2 Results......Page 110
5.3 Thermal driven floorplanning......Page 111
5.3.1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning......Page 113
5.3.2 Coupled Temperature and Leakage Estimation......Page 117
5.3.3 2.5-D Thermal Driven Floorplanning Techniques......Page 123
5.3.4 Experimental results......Page 125
5.4 Observations......Page 129
References......Page 131
6 Placement for 2.5-D Integration......Page 135
6.1 Pure Standard Cell Designs......Page 137
6.1.1 Placement Techniques......Page 138
6.1.2 Benchmarks and Layout Model......Page 141
6.1.3 Evaluation of Vertical Partitioning Strategies......Page 143
6.1.4 Wire length scaling......Page 144
6.1.5 Wire length reduction......Page 147
6.1.6 Wire Length vs. Inter-Chip Contact Pitch......Page 151
6.2 Mixed Macro and Standard Cell Designs......Page 152
6.2.1 Placement Techniques......Page 154
6.2.2 Results and Analysis......Page 156
6.3 Observations......Page 158
References......Page 160
7 A Road map of 2.5-D Integration......Page 162
7.1 Stacked Memory......Page 163
7.2 DRAM Integration for Bandwidth-Demanding Applications......Page 165
7.3 Hybrid System Integration......Page 169
7.4.1 Highly Integrated Image Sensor System......Page 173
7.4.2 Radar-in-Cube......Page 176
References......Page 178
8 Conclusion and Future Work......Page 182
8.1 Main Contributions and Conclusions......Page 183
8.2 Future Work......Page 186
8.2.1 Fabrication Technology for 2.5-D Systems......Page 187
8.2.2 Testing Techniques for 2.5-D Integration......Page 189
8.2.3 Design Technology for 2.5-D Integration......Page 191
8.2.3.1 2.5-D Architecture Exploration tools......Page 192
8.2.3.2 System Level Design Tools......Page 196
8.2.3.3 Physical Design Tool Suite for 2.5-D ASICs......Page 197
8.2.3.4 2.5-D VLSI Design Flow......Page 201
References......Page 204
Index......Page 206

Details

  • Author: Yangdong Deng, Wojciech P. Maly
  • Edition: 1st Edition.
  • Publication Date: 2010
  • Publisher: Springer
  • ISBN-10: 3642041566
  • ISBN-13: 9783642041563, 9787302211655
  • Pages: 212
  • Format: pdf
  • Size: 4.7M
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